Electro-Magnetic Interference (EMI) has emerged as a challenging issue to tackle in the field of digital products including Flat Panel Displays (FPDs) that have been increased in their sizes and usages. Along with an increase in the resolution of displays such as TV or monitors, the demand for transmission of more and more data is also on the increase.
For example, when data is transmitted at high data rate to meet the demand for large-scale data transmission, much EMI occurs. The EMI is especially great at a transmission line in which data signals are transmitted between a timing controller and a source driver in a column driving Integrated Circuit in an FPD.
Among methods for overcoming EMI, there is a method for distributing the EMI of a specific frequency band to adjacent frequency bands by spreading the frequency of a synchronization clock signal of a logic circuit. This is called spread spectrum clock generation.
FIG. 1 is a block diagram of a related data transmission apparatus using spread spectrum clock generation. Referring to FIG. 1, the transmitter includes D flip-flops (f/fs) 10 and 16, a First Input First Output (FIFO) memory 12, and a Spread Spectrum Clock Generator (SSCG) 14. The D f/f 10 outputs input data to the FIFO memory 12 in response to a first latch clock signal CLKI.
The data transmission apparatus illustrated in FIG. 1 is used in the timing controller of a related FPD. The data transmission apparatus may use the SSCG 14 inside or outside of the IC in order to decrease an overall EMI level by spreading the EMI of a specific frequency caused by the first latch clock signal CLKI band to adjacent frequency bands.
To prevent data transmission errors that may be generated due to a changed clock domain, the data transmission apparatus further includes the FIFO memory 12 for storing a predetermined amount of data. The size of the FIFO memory 12 is determined according to a modulation frequency and a modulation rate that controls the SSCG 14.
FIGS. 2(a), 2(b) and 2(c) are waveform diagrams of components illustrated in FIG. 1. FIG. 2(a) is a waveform diagram of a second latch clock signal generated from the SSCG 14, FIG. 2(b) is a waveform diagram of data output from the D f/f 10, and FIG. 2(c) illustrates the spectrum of the second latch clock signal. In FIG. 2(c), the horizontal axis represents frequency and the vertical axis represents signal amplitude, i.e. signal level.
Referring to FIGS. 2(a), 2(b) and 2(c), it is noted from an output modulation signal and its frequency spectrum that the data transmission apparatus illustrated in FIG. 1 mitigates EMI by use of the SSCG 14. That is, the afore-mentioned effect of spread spectrum is observed. However, the related data transmission apparatus suffers from the following drawbacks.
In the data transmission apparatus illustrated in FIG. 1, the input and output of the SSCG 14 are inevitably in different synchronization clock domains. Accordingly, the FIFO memory 12 is required to be of an infinite size in theory. Even though only a specific amount of data can be stored in the FIFO memory 12 by restricting the modulation frequency and the modulation rate, data transmission is enabled.
However, available modulation frequencies and modulation rates are limited. Moreover, to secure a modulation frequency and modulation rate of a specific level for EMI mitigation, the capacity of the FIFO memory 12 must be sufficient. Use of an FIFO memory 12 with insufficient capacity leads to data transmission errors. Considering that a modulation frequency ranges from tens of kHz to hundreds of kHz and a modulation rate is several %, a large memory space is required. Consequently, the FIFO memory 12 must increase in size.
In addition, the related data transmission apparatus described above has the SSCG 14 outside of the IC, for frequency modulation of a synchronization clock signal. Thus, the overall throughput of a product decreases. Even if the SSCG 14 is integrated into the IC, the size of the SSCG 14 increases due to the FIFO memory 12, thereby decreasing product competitiveness and throughput.